Hetero-junction bipolar transistor and the method for producing the same

ABSTRACT

This invention provides a hetero-junction bipolar transistor with a new structure that prevent the corrector resistance from increasing as shrinking the size of the transistor. The bipolar transistor according to the invention comprises a substrate  2 , a collector layer  6   a , a base layer  10   a  and an emitter layer  12   a . The collector layer  6   a  is formed on a first region of the substrate. The base layer  10   a  is formed on a second region of the substrate and has band gap energy smaller than that of the collector layer  6   a  and that of the emitter layer  12   a . The plan shape of the first region is substantially same as that of the second region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a hetero-junction bipolar transistor and a method for producing the hetero-junction bipolar transistor.

2. Related Prior Art

A hetero-junction bipolar transistor (HBT) is made of group III-V compound semiconductors and shows a high current gain, a superior high-frequency performance and a high-speed switching capability. One type of the HBT has an emitter with band gap energy greater than that of a base. Another type of the HBT is a hetero junction transistor with a double hetero junction (DHBT), in which the band gap energy of the base is smaller than that of the emitter and the collector.

To enhance the high frequency performance of the HBT requires shrinking a size of the transistor. Typical DHBT has a sub-collector made of InGaAs, a collector made of InP, a base made of InGaAs, an emitter made of InP and an emitter-contact made of InGaAs, and these layers are grown on an InP substrate. When the collector made of InP is etched with an etching mask same as that used at the etching for the base layer, a size of the collector layer becomes smaller than that of the base layer because a thickness of the collector layer is in general thicker than that of the base layer and a side etching of the collector layer appears. Due to this side etching of the collector, an intrinsic collector, through which a current from the emitter flows, becomes small when making the small-sized transistor, thereby increases a collector resistance, which reduces the current gain, the high frequency performance and the high speed switching. One object of the present invention is to provide a HBT, which avoids the increasing of the collector resistance, and a method for producing the HBT.

SUMMARY OF THE INVENTION

One feature of the present HBT comprises a semiconductor substrate, a collector layer, a base layer and an emitter layer. Band gap energy of the base layer is smaller than that of the collector layer and the emitter layer. The collector layer is defined by a first type of sides extending along [011] crystal orientation, a second type of sides along [01-1] orientation, and a third type of sides along [010] orientation shorter than the first type of sides and the second type of sides.

Another feature of the HBT according to the present invention is that the HBT comprises the base layer that has a plan shape defined by a fourth type of sides extending along [011] orientation, a fifth type of sides along [01-1] orientation, and sixth type of sides along [010] orientation. The ratio of a length of the third type of sides of the collector layer to than of the sixth type of sides of the base layer is greater than 0.9 and smaller than 1.5.

Still anther feature of the HBT according to the present invention is that the HBT comprises a semiconductor substrate and a multiple layers of a collector layer, a base layer and an emitter layer, they are disposed on the semiconductor substrate. Band gap energy of the base layer is smaller than that of the collector layer and that of the emitter layer. The collector layer is formed on a first region of the substrate and defined by a first type of sides extending along [011] orientation, a second type of sides along [01-1] orientation, and a third type of sides along [010] orientation. The base layer is formed on a second region of the substrate, which is substantially same with the first region.

These HBT suppress the increasing of the collector resistance due to a shrinking of their size. The HBT according to the present invention may have InP for the substrate, the collector layer and the emitter layer, while InGaAs for the base layer.

Another aspect of the present invention relates to a method for producing the HBT. The method comprises: a) sequentially growing a first semiconductor film for the collector layer, a second semiconductor film for the base layer and a third semiconductor film for the emitter layer on the semiconductor substrate; b) processing the third film to the emitter layer and the second film to the base layer by using a first mask; c) forming a second mask on the first semiconductor film so as to cover the base layer and the emitter layer; and d) processing the first semiconductor film to the collector layer by using the second mask. The second mask is demarcated by a first type of edges extending along [011] orientation, a second type of edges along [01-1] orientation and a third type of edges along a predetermined orientation that crosses one of the first type of edges and the second type of edges.

Since the third film and the second film are processed with the first mask and the first film is processed with the second mask, a shape of the second mask may be so formed that the plan shape of the collector layer corresponds to that of the base layer.

In the method, the predetermined axis may extend along [010] direction, or may extend along the direction not across one of the first type of edges and the second type of edges.

Further in the method according to the present invention, preceding to the processing of the third film to the emitter layer and the second film to the base layer, the first mask is formed on the third semiconductor film. The first mask comprises a plurality of edges extending along directions different to [010] orientation.

In the present method, the first film for the collector layer may be made of InP and processed by a solution including hydrochloric acid.

BRIEF DESCRIPTION OF DRAWINGS

From FIG. 1A to FIG. 1C are cross sectional views illustrating the process for the HBT of the present invention;

FIG. 2A is a plan of the emitter-contact mesa, FIG. 2B is a cross sectional view taken along the line I-I in FIG. 2A, and FIG. 2C is a cross sectional view taken along the line II-II;

From FIG. 3A to FIG. 3C show the emitter-base mesa;

FIG. 4 is a plan view showing the emitter-base mesa;

From FIG. 5A to FIG. 5B are sectional views showing the formation of the etching mask for the collector layer;

FIG. 6A is a plan view showing the etching mask for the collector layer, and FIG. 6B shows the formation of the collector mesa;

From FIG. 7A to FIG. 7C illustrate the appearance of the collector layer as the etching proceeds;

FIG. 8A and FIG. 8B are cross sectional view showing the collector layer.

FIG. 9A illustrates the plan view of the collector layer after the etching, and FIG. 9B is a perspective view of the collector layer;

FIG. 10A and FIG. 10B are plan view and a perspective view processed by the conventional etching mask without any projective portions;

FIG. 11A and FIG. 11B are cross sectional views showing the sub-collector layer;

FIG. 12A and FIG. 12B show the process for forming the electrode of the collector, the base and the emitter;

FIG. 13 is a plan view of the transistor with wiring;

FIG. 14A is a cross sectional view taken along the line III-III in FIG. 13, and FIG. 14B is a cross sectional view along the line IV-IV in FIG. 13;

From FIG. 15A to FIG. 15D show modified patterns of the photo-mask used for the first embodiment; and

From FIG. 16A to FIG. 16D are another modified patterns of the photo-mask for the first embodiment.

DETAILE DESCRIPTION OF THE INVENTION

Next, preferable embodiments for a manufacturing method of a hetero-junction bipolar transistor according to the present invention will be described as referring to accompanying drawings. In drawings, Elements identical to each other will be referred to with numerals identical to each other without overlapping explanations.

First Embodiment

Figures from FIG. 1A to FIG. 1C show cross sectional views of a double-hetero-junction bipolar transistor (hereinafter denoted by DHBT) at manufacturing steps. As shown in FIG. 1A, a semi-insulating InP substrate 2 is prepared. The substrate has a primary surface 2 a with a (100) crystal surface.

(Crystal Growth)

FIG. 1B shows semiconductor layers grown on the substrate 2. A series of semiconductor films of a sub-collector film 4, a collector film 6, a graded-collector film 8, a base film 10, an emitter film 12, and an emitter-contact film 14, are sequentially grown on the substrate. An organo-metallic vapor phase epitaxy (OMVPE) technique performs the growth of these films. Triethyl Gallium (TEGa), Trimethyl Indium (TMIn), Arsine (AsH₃) and Phosphine (PH₃) are used for source materials of the OMVPE. Compositions, dopant materials, thickness and carrier concentrations of respective films are shown in the following table. Composition of ternary material (InGaAs) and that of quo-ternary material (InGaAlAs) are selected so that a lattice constant thereof matches to that of InP within ±0.1%. TABLE 1 Carrier Thickness Concentration Film Material Dopant (nm) (cm⁻³) sub-collector film 4 InGaAs Si 300 2 × 10¹⁹ collector film 6 InP — 330 −z graded-collector film 8 InGaAlAs Si 50 1 × 10¹⁷ base film 10 InGaAs C 50 4 × 10¹⁹ emitter film 12 InP Si 10 4 × 10¹⁸ emitter-contact film 14 InGaAs Si 250 4 × 10¹⁹

The sub-collector film 4, the graded-contact film 8, the emitter film 12 and the emitter-contact film 12 are n-type semiconductor containing Si with a dopant material. Doping source for the n-type dopant is Silane (SiH4) is used. By increasing the carrier concentration of the emitter-contact film 14, a good ohmic contact between the emitter-contact film 14 and an emitter electrode may be obtained.

On the other hand, carbon (C) atoms may be used in the base film 10 as a p-type dopant. Doping source is Carbon-bromide (CBr₄). By using carbon as the p-type dopant, the hole concentration in the base film 10 can be increased, which improves the high-frequency performance of the DHBT. Diethyl Zinc (DEZn) may be substitutable for CBr₄.

(First Mesa Formation)

FIG. 1C shows a formation of the first mesa. The first mesa involves an emitter contact layer. An etching mask 18 made of an inorganic material, such as SiN, is formed on the emitter contact film 14 by a photolithography technique. Dipping the substrate into an etchant including a phosphoric acid and a hydrogen peroxide, a disposed portion from the etching mask 18 of the emitter contact film 14 is removed. Since the above etchant etches the InGaAs film of the emitter contact 14 selectively to the emitter film made of InP, only the emitter contact film 14 may be removed. An emitter contact layer 14 a thus processed is formed on the emitter film 12 as shown in figures from FIG. 2A to FIG. 2C.

FIG. 2A is a plan view showing the emitter-contact layer 14 a formed by the process above described. FIG. 2B is a cross sectional view taken along the line I-I in FIG. 2A, and FIG. 2C is another cross sectional view taken along the ling II-II in FIG. 2A. The emitter-contact layer 14 a has a pair of side surfaces 14 b and 14 c extending along [01-1] crystal orientation, and a pair of side surfaces 14 d and 14 e extending along [011] crystal orientation. In the present embodiment, the plan shape of the emitter-contact layer 14 a is a nearly rectangle and formed on the emitter film 12.

(Second Mesa Formation)

Figures from FIG. 3A to FIG. 3C illustrate the manufacturing step of the second mesa formation. The second mesa includes an emitter layer 12 a, a base layer 10 a and a graded-collector layer 8 a. Referring to FIG. 3A, an etching mask 20, which may be made of an inorganic material such as SiN and processed by the photolithography technique, is formed on the base film 12. The mask 20 is formed on the emitter film so as to cover the emitter-contact layer 14 a.

By using a hydrochloric acid as an etchant, a portion of the emitter film 12 not covered by the mask 20 is etched selectively to the base film 10 made of InGaAs. Namely, the etching rate of this etchant for InGaAs is quite small as compared to that for InP. This etching process forms an emitter layer 12 a as shown in FIG. 3A.

Subsequently to the forming the emitter layer 12 a, another etchant of a mixture of phosphoric acid and hydrogen peroxide etches the base film 10 and the graded-collector film 8. Contrary to the first etchant of the hydrochloric acid, the second etchant shows an etching selectivity of the InGaAs or InGaAlAs to InP, namely the etching rate of the second etchant for InP is quite small compared to that for InGaAs or InGaAlAs. This second etching of the base film 10 and the graded-collector film 8 forms a base laser 10 a and a graded-collector layer 8 a on the collector film 6, as shown in FIG. 3C.

FIG. 4 is a plan view showing the emitter-base mesa 22 formed by the etching process above described with the etching mask 20 is removed. The emitter-base mesa 22 comprises the emitter layer 12 a, the base layer 10 a and the graded-collector layer 8 a. The plan shape of the etching mask 20 is nearly rectangle with four corners from 20 a to 20 d, a pair of edges extending along [011] crystal orientation and a pair of edges extending along [01-1] crystal orientation. While undercuts are formed at respective corners of the mask 20 and the plan shape of the emitter-base mesa is substantially octagonal. Consequently, the emitter-base mesa has a first pair of side edges 22 a and 22 b extending along [011] crystal orientation, a second pair of side edges 22 c and 22 d along [01-1] crystal orientation, and four side edges from 22 e to 22 h extending along [010] crystal orientation and its equivalent. The plurality of side edges 22 e to 22 h respectively connects to the corresponding side edges. For example, the side edge 22 e connects the first side edge 22 a to the second side edge 22 c.

(Etching Mask Formation)

From FIG. 5A to FIG. 6B show process steps of forming an etching mask for the collector film. Referring to FIG. 5A, an inorganic film 24, such as SiN, is formed so as to cover the collector film 6, the emitter-base mesa 22 and the emitter contact layer 14 a. A photo-resist 26 is formed on the inorganic film 24 and processed in photolithography to a specific plan shape by a photo mask 30 shown in FIG. 6A. The inorganic film 24 is dry-etched by using the etching mask 26. After removing the photo-resist 26, the inorganic film 24 with the specific plan shape can be obtained.

FIG. 6A is a plan view showing a photo-mask pattern 28 for the etching of the collector film 6. The photo-mask pattern 28 comprises a region R (hereinafter denoted as the first region) and a plurality of subsidiary regions from T₁ to T₄ (hereinafter denoted by the second regions). The first region R reflects a collector layer to be formed and has a pair of sides S₁₁ and S₁₃ extending along [01-1] crystal orientation, and another pair of sides S₁₂ and S₁₄ extending along [011] orientation. The second regions from T_(1 to T) ₄ are triangles formed by sides S₁ and S₂, which forms an acute angle to each other, and another side S₃ is denoted by broken lines. The second regions T₁ to T₄ are in contact with the first region R. Namely, as shown in FIG. 6A, the side S₃ of the region T₁ is in contacts with the side S₁₁ of the first region and falls on a line 28 a, on which the side S₁₂ of the first region R falls, too. Similarly, the side S₃ of the second region T₄ is in contact with the side S₁₃ of the first region and the side S₁ falls on a line 28 a. The side S₁₂ of the first region R comprises a line combined with the side S₁ of the region T₁ and the side S₁ of the region T₄. The side S₃ of one of the second region T₂ is in contact with the S₁₁ of the first region R and the side S₁ of the second region T₂ falls on a line 28 b. The side S₁₄ of the first region comprises a line combined with the side S₁ of the second region T₂ and the side S₁ of the second region T₃. As shown in FIG. 6A, the second regions from T₁ to T₄ are respectively located so that points intersecting lines S1 and S3 are aligned to corresponding points from 28 c to 28 f of the first region R.

Referring back to FIG. 5B, a cross sectional view after the etching of the inorganic film 24 by using the photo-resist 26 is illustrated. The inorganic film 24 is processed to an etching mask 32. FIG. 6B is a plan view showing the processed inorganic film 32, the emitter-base mesa 22 and the emitter contact layer 14 a. The processed inorganic film 32 covers not only the emitter contact layer 14 a but also the emitter-base mesa 22, thereby protects the emitter-base mesa 22 from being etched at the subsequent process. The shape of the processed inorganic film 32 approximately reflects the photo-mask pattern, but the corners thereof are blunted due to lack of the resolution.

The processed inorganic film 32 has edges from 32 a to 32 d each extending along corresponding edges 22 a to 22 d of the emitter-base mesa. Further, the film 32 has two portions 32 e and 32 f each projected from the side 32 c and another two portions 32 g and 32 h each projected from the side 32 d. These projected portions from 32 e to 32 h are aligned to edges from 22 e to 22 h of the emitter-base mesa extending along [010] crystal orientation. Typical dimensions D_(1 and D) ₂ of the projection are about 0.3 μm.

(Third Mesa Formation)

After processing the inorganic film 32, the substrate 2 is immersed in a solution of hydrochloric acid. The portion not covered by the inorganic film 32 of the collector film 6 is removed. This etchant etches the collector film made of InP selectively to the sub-collector film made of InGaAs. Therefore, the etching substantial stops after the surface of the sub-collector film is exposed.

From FIG. 7A to FIG. 7C are views showing SEM photographs taken as the etching of the collector film is performed. FIG. 7A shows an appearance of the collector film 61 after the etching of 80 seconds, in which edges of the collector film 61 under the corresponding corners from 32 e to 32 h of the inorganic film 32 are selectively removed. FIG. 7B shows an appearance after the etching of 120 seconds, in which edges under the respective corners of the film 32 are removed further. This peculiar etching behavior reflects the intrinsic characteristic of the semiconductor material with a zinc-blend crystal structure, in which the etching rate along [001] crystal orientation is larger than that along [011] crystal orientation. FIG. 7C shows an appearance after the etching of 160 seconds, in which the plan shape of the collector film 63 is nearly same as that of the emitter-base mesa 22.

Comparing the appearance of the collector film 63 in FIG. 7C to that shown in FIG. 7A, side edges extending along [011] crystal orientation are little etched. This inhomogeneous etching characteristic shows that, when the dimension of the projected regions from T_(1 to T) ₄ of the photo-mask 28 are defined depending on the thickness of the collector film 6, the position of the edges of the collector layer 63 can be adjusted to that of the emitter-base mesa 22. In the etching of the collector film 6, since the processed inorganic film 32 covers the side surface of the emitter-base mesa 22, layers from 8 a to 12 a within the emitter-base mesa are not affected by the etching. In FIG. 8A and FIG. 8B, cross sectional views at the etching of the collector film 6 are shown. By the etching above described, the collector film is converted to the collector layer 6 a, which is the collector mesa 33.

FIG. 9A is a plan view showing the collector mesa 33 after the etching and FIG. 9B is a perspective view of the collector mesa 33. As shown in figures, side surfaces 33 a and 33 b, which extends along [01-1] crystal orientation, of the collector mesa 33 has a normal mesa surface, where (111) surface is appeared. On the other hand, the edge 33 d extending along [011] crystal orientation has a reverse mesa surface 33 d, where (1-1-1) surface is appeared, and anther edge 33 c extending along [001] exposes (001) surface.

FIG. 10A and FIG. 10B show the shape of the collector mesa 34 when the etching of the collector film 6 to form the collector mesa is performed by using an etching mask without projected regions. The collector layer 34 a in FIG. 10A and FIG. 10 b is considerably side-etched under the emitter-base mesa 34 b. Comparing the shape of the collector mesa in FIG. 10A to that in FIG. 9A, the side edge of the collector layer 34 a extending along [001] crystal orientation is far from the side edge of the emitter-base mesa along [001] orientation and is close to the side edge of the emitter contact mesa 34 c. Therefore, when the size of the transistor is shrunk, the collector resistance may increase due to the shape of the collector layer.

(Sub-Collector Mesa Formation)

FIG. 11A and FIG. 11B are cross sectional views showing a process for forminig the sub-collector mesa. First, an etching mask 36 is formed so as to cover the collector layer 6 a, the emitter-base mesa 22 and the emitter-contact layer 14 a. In this embodiment, the mask 36 is made of a photo-resist.

After forming the mask 36, the substrate is immersed to a mixture of phosphoric acid and hydrogen peroxide. This etchant etches InGaAs selectively to InP; namely, the etching rate for InP is far small compared to that for InGaAs. Therefore, after exposing the InP substrate, the etching substantial stops. By this etching, the sub-collector film 4 is converted to the sub-collector layer 4 a. Another etchant, such as a mixture of sulfuric acid and hydrogen peroxide, may be used instead of the mixture of phosphoric acid and hydrogen peroxide. The sub-collector layer 4 a electrically isolates the transistor thus formed from transistors formed adjacently on the substrate.

(Electrode Formation)

Next, the process for forming electrodes of the collector, the base and the emitter will be described. Referring to FIG. 12A and FIG. 12B, an inorganic film 38 such as SiN is formed to cover the sub-collector layer 4 a, the base layer 12 a and the emitter contact layer 14. A photo-resist 40 with an etching pattern is formed on the inorganic film 38. The etching pattern has openings 40 a and 40 b on the sub-collector layer 4 a, the base layer 12 a and the emitter contact layer 14 a. The opening 40 a is for the emitter electrode and the base electrode while the opening 40 b is for the collector electrode.

After forming the photo-resist 40, a series of metals of titanium (Ti), platinum (Pt) and gold (Au) are sequentially stacked on the photo-resist and within the openings 40 a and 40 b. In the opening 40 a, since the emitter contact layer has side edges of the reverse mesa extending along [011] crystal orientation, metals are not deposited on the emitter layer 12 a under the overhang of the emitter contact mesa 14 a. Therefore, the emitter electrode 52 a on the emitter contact layer 14 a and the base electrode 42 b on the emitter layer 12 a are separated in self-alignment.

Metals 42 d on the photo-resist 40 are removed at the same time of the dissolution of the photo-resist 40, which is called the lift-off method. Thus, the electrodes of the emitter, the base and the collector are formed. Subsequently to the electrode formation, an inorganic film 56 such as SiN is deposited on the substrate to passivate respective electrodes. In the passivation film 56, several via-holes are processed to contact electrically to respective electrodes, and on the film 56, wiring from the via-hole is deposited. FIG. 13 is a plan view of the transistor thus processed and FIG. 14A and FIG. 14B are cross sectional views taken along the line III-III and the line IV-IV in FIG. 13, respectively.

In FIG. 13, the transistor 1 a comprises the semiconductor substrate 2 a, the sub-collector layer 4 a, the collector layer 6 a, the graded-collector layer 8 a, the base layer 10 a, the emitter layer 12 a and the emitter-contact layer 14 a. Exemplary configuration is that the band gap energy of the sub-collector layer 4 a is smaller than that of the collector layer 6 a, the band gap energy of the base layer 10 a is smaller than that of the emitter layer 12 a and also the collector layer 6 a, and the band gap energy of the emitter-contact layer 14 a is smaller than that of the emitter layer 12 a. The transistor 1 a has the base electrode 44, the collector electrode 46 and the emitter electrode 48. The transistor further has the emitter wiring 50, the base wiring 52 and the collector wiring 54.

The substrate 2, the collector layer 6 a and the emitter layer 12 a may be made of InP, while the base layer 10 a may be InGaAs. The collector layer 6 a of the present transistor is demarcated by eight sides and the base layer 10 a is also demarcated by eight sides, they corresponds to respective eight sides of the collector layer 6 a and extends along the same direction as that of the collector 6 a. The area of the collector layer 6 a in this embodiment is substantially same as that of the base layer 10 a. However, taking the fluctuation of the process condition into account, a ratio of the collector layer 6 a to that of the base layer 10 a may be greater than 0.9 and little than 1.1.

Another aspect of the present invention, the collector layer 6 a of the transistor 1 a is demarcated by the side 6 b along [011] orientation, the side 6 c along [01-11] orientation and the ling 6 d along [010] orientation. The side 6 d is shorter than the side 6 b and the side 6 c. On the other hand, the base layer 10 a is demarcated by the side 10 b along [011] orientation, the side 10 c along [01-1] orientation, and the side 10 d along [010] orientation. The side 10 d is shorter than the side 10 b and the side 10 c.

Taking the fluctuation of the process condition into account, it is considered that the side 6 d of the collector layer 6 a may position in the inside of the side 10 d of the base layer. When the collector film 6 is over-etched, the side 6 d of the collector layer 6 a is in the inside of the side 10 d of the base layer 10 a. The ratio of the side 10 d of the base layer 10 a to the side 6 d of the collector layer 6 a may be greater than 0.9 and smaller than 1.5. The transistors, in which the collector layer and the base layer has the relation above described, show a relative small collector resistance, thereby enhances performance of the transistor especially in high frequencies.

Second Embodiment

In the second embodiment, patterns of the photo-mask used in the etching of the collector film are described.

FIG. 15A shows the first pattern 28 of the photo mask used in the first embodiment. From FIG. 15B to FIG. 15D, various substitutional patterns are illustrated. By using these patterns, the prescribed shape described in the first embodiment can be obtained. In figures, first lines along the X-direction, second lines along the Y-direction and a plurality of lines crossing one of the first line and the second line define these patterns, where the X-direction and the Y-direction coincide with [011] crystal orientation and [01-1] crystal orientation, respectively.

Referring to FIG. 15B, the pattern 66 comprises a first portion R₁ and a plurality of second portions from U_(1 to U) ₄. The portion R₁ corresponds to the collector layer to be formed. Respective portions from U₁ to U₄are aligned to corners from 66 c to 66 f of the first portion R₁. Similarly, the pattern 68 in FIG. 15C and the pattern 70 in FIG. 15D comprise the first portion R₂, R₃ and a plurality of second portions V₁ to V₄, W1 to W₄, respectively. Moreover, respective second portions locate at the corner, from 68 c to 68 f and from 70 c to 70 f, of the respective first portion.

The second portion, U_(1 to U) ₄, V₁ to V₄ and W₁ to W₄ and have a substantially triangle shape, which comprise a pair of side S1 and S2 making an acute angle to each other and another side, which connects the side S1 to the side S2 and illustrated by a broken line in figures. Portions from U₁ to U₄ are in contact with the portion R₁, portions from V₁ to V₄ are in contact with the portion R₂, and portion W_(1 to W) ₄ are in contact with the portion R₃. The respective second portion are shaped so as to form projected portions, 32 e to 32 h, in FIG. 7 and is aligned to side edges, 22 e to 22 h, extending along [010] orientation of the emitter-base mesa in FIG. 6.

Other modified patterns are illustrated in figures from FIG. 16A to FIG. 16D. These patterns also realize the expected shape of the collector layer. Namely not only the triangle but also substantially rectangle of the second portion may be applicable. Referring to FIG. 16A, the pattern 72 comprises a substantially rectangle portion R₄ and a plurality of rectangle portions from X₁ to X₄, which are called the first portion and second portions, respectively. The first portion R₄ relates to the collector layer to be formed. Second portions from X₁ to X₄ are each aligned to corners from 72 c to 72 f of the first portion R₄. The portion R₅ and portion from Y_(1 to Y) ₄ illustrated in FIG. 16B, the portion R₆ and portions from Z₁ to Z₄ in FIG. 16C, and the portion R₇ and portions from Q_(1 to Q) ₄ in FIG. 16D have similar relation to that illustrated in FIG. 16A and described above.

The manufacturing method of the HBT is thus described as referring to exemplary embodiment. It will be obvious that the invention and its application may be varied in many ways. One alternation is that the length of sides S1 and S3 of portions from T1 to T4 in FIG. 15 are appropriately adjustable. Shapes of the second portions from T_(1 to T) ₄ are not restricted to the shape illustrated in FIG. 15 and FIG. 16. Moreover, the size of the second portion defined by and depends on characteristics of the collector layer, such as a thickness, a width and a length thereof. Namely, the size and the shape of the etching mask are preferably defined so that the size and the shape of the collector layer to be formed substantially coincide with that of the base layer. The manufacturing method of the present invention is not restricted for the InP-based HBT but for the GaAs-Based HBT formed on the GaAs substrate and uses the combination of AlGaAs emitter layer and GaAs base layer.

Further, the method of the etching for the respective films are exemplary and the process are not restricted to the described method. Although semiconductor films are grown by the MOCVD, the method of the growing is not restricted. Another method, such as Chemical Beam Epitaxy (CBE), is also applicable. 

1. A hetero-junction bipolar transistor, comprising: a semiconductor substrate made of a first compound semiconductor material with a first band gap energy; a collector layer made of a second compound semiconductor material with a second band gap energy, the collector layer having a plan shape defined by a first type of sides extending along [011] orientation, a second type of sides extending along [01-1] orientation and a third type of sides extending along [010] orientation shorter than the first type of sides and the second type of sides; a base layer made of a third compound semiconductor material with a third band gap energy; an emitter layer made of a fourth compound semiconductor material with a fourth band gap energy; wherein the third band gap energy of the base layer is smaller than the second band gap energy and the fourth band gap energy.
 2. The hetero-junction bipolar transistor according to claim 1, wherein the base layer further has a plan shape defined by a fourth type of sides extending along [011] orientation, a fifth type of sides extending along [01-1] orientation, a sixth type of sides extending along [010] orientation, and wherein a ratio of a length of the third type of sides of the collector layer to a length of the sixth type of sides of the base layer is greater than 0.9 and smaller than 1.5
 3. The hetero-junction bipolar transistor according to claim 1, wherein the second semiconductor material and the fourth semiconductor material are InP, and the third semiconductor material is InGaAs.
 4. A hetero-junction bipolar transistor, comprising: a semiconductor substrate made of a first semiconductor material, the substrate having a first region and a second region on a primary surface; a collector layer formed in the first region of the substrate and made of a second semiconductor material with a first band gap energy, the collector layer being defined by a first type of sides extending along [011] orientation, a second type of sides extending along [011] orientation and a third type of sides extending along [010] orientation; a base layer formed in the second region of the substrate and made of a third semiconductor material with a second band gap energy smaller than the first band gap energy; and an emitter layer made of fourth semiconductor material with a third band gap energy greater than the second band gap energy of the base layer, the emitter layer formed on the substrate, wherein the second region is substantially same as the first region.
 5. A method for producing a hetero-junction bipolar transistor having a collector layer, a base layer and an emitter layer on a semiconductor substrate, band gap energy of the base layer is smaller than band gap energy of the collector layer and the emitter layer, the method comprising the steps of: a) sequentially growing a first semiconductor film of the collector layer a second semiconductor film of the base layer and a third semiconductor film of the emitter layer on the semiconductor substrate; b) processing the third film to the emitter layer and the second film to the base layer by using a first mask; c) forming a second mask on the first semiconductor film so as to cover the base layer and the emitter layer; d) processing the first semiconductor film to the collector layer by using the second mask, wherein the second mask is demarcated by a first type of edges extending along [011] orientation, a second type of edges extending along [01-1] orientation and a third type of edges extending along a predetermined orientation crossing one of the first type of edges and the second type of edges.
 6. The method according to claim 5, wherein the predetermined axis extends along [010] orientation.
 7. The method according to claim 5, wherein the predetermined axis extends along the other of the first type of edges and the second type of edges.
 8. The method according to claim 5, further comprises a step of, preceding the processing of the third film to the emitter layer and the second film to the base layer forming, forming the first mask on the third semiconductor film, wherein the first mask comprises a plurality of edges extending along directions different to [010] orientation.
 9. The method according to claim 5, wherein the first film is made of InP and processed by a solution including hydrochloric acid at step d). 